Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 157

MV 4 , MV 6 ) are devices in the QCA layout of the Fredkin gate that are

making the design untestable by all 0s and all 1s test vectors. This work focuses
on demonstrating the fault tolerant QCA circuits that provide ease of testability
as the proposed sequential building blocks can be tested using only two test
vectors. In the existing literature, several fault tolerant QCA components have
been proposed such as Majority voters (MVs), Inverters (INVs), Fanouts (FOs),
Crosswires (CWs) and L-shape wires (LSWs) [ 12 , 15 , 16 , 74 ]. Thus, these devices
can be replaced by their fault tolerant counterparts in the QCA layout of the
Fredkin gate to have the equivalent design that gives 100 % fault coverage to
test vectors all 1s and all 0s. The HDLQ model of the Fredkin gate QCA layout
having 100 % coverage for any single missing/additional cell defect to test vectors
all 0s and all 1s is shown in Fig. 20 . In Fig. 20 , the shaded devices represent their
fault tolerant counterparts. Thus, conservative logic QCA circuits based on our
proposed QCA layout of the Fredkin gate show in Fig. 20 , can be tested by all
0s and all 1s test vectors for presence single missing/additional cell defects.

MV 5 and

Fig. 20. QCA layout of the Fredkin gate testable with only all 0s and all 1s test vectors
for any single missing/additional cell defect (the shaded devices represent their fault
tolerant counterpart)