Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 143

3.2 Design of Testable Reversible T Latch

+ =(

The characteristic equation of the T latch can be written as Q T · Q ) · E +

¯

+ =(

E · Q .The

T(toggle) latch is a complementing latch which complements its value when
T = 1, that is when T = 1 and E = 1 we have

. But the same result can also be obtained from Q T · E ) ⊕ Q

+ =Q ₓ . When T = 0, the T latch
maintains its state and we have no change in the output. Figure 9 (a) shows the
proposed design of reversible testable T latch with C1, C2, and C3 as control
signals. The control signal C3 helps to realize the reversible AND function as
we can generate

Q

when C3 = 0, at one of the outputs of the Fredkin gate
as illustrated in Fig. 9 (b). C1 and C2 are the main control signals that help
in breaking the feedback to make the design testable as well as in enabling
the normal mode of operation. In normal mode, as illustrated in Fig. 9 (b), the
values of the control signals will be C1 = 0 and C2 = 1 thus helping in realizing
the function (

T · E

. In test mode, when C1 = 0 and C2 = 0 as shown in
Fig. 9 (d) it will break the feedback and test the design with all 0s test vector
for any stuck-at-1 fault, while when C1 = 1 and C2 = 1 as shown in Fig. 9 (c) it
will break the feedback and helps in testing the design with all 1s test vector
for any stuck-at-0 fault. The other types of reversible testable latches based
on conservative reversible logic such as the JK latch and the SR latch can be
designed similarly, thus are not discussed in this work.

T · E ) ⊕ Q

3.3 Design of Testable Asynchronous Set/Reset D Latch

The design of the asynchronously set/reset D latch is shown in Fig. 10 (a).
The design has 3 Fredkin gates. We can observe that the first Fredkin gate
maps the D latch characteristic equation, while the second and the third Fred-
kin gates take care of the fan-out and also help in asynchronous set/reset of
the output Q. The design has two control inputs C1 and C2. When C1 = 0 and
C2 = 1, the design works in normal mode implementing the D latch characteris-
tic equation. When C1 = 0 and C2 = 0, the second and third Fredkin gates will
reset the output Q to 0. When C1 = 1 and C2 = 1, the design will be set to
Q = 1. Thus, the control inputs help the design to work in various modes. But
the design shown in Fig. 10 (a) has fan-out of more than one in C1 and C2 inputs
which is prohibited in reversible logic. Thus, a modified design of the D latch
with asynchronous set/reset capability in which there is no fan-out is shown in
Fig. 10 (b). There is a special characteristic of the reversible D latch design shown
in Fig. 10 (b). The design shown in Fig. 10 (b) has the control signals C1 and C2
which helps in disrupting the feedback. For example, the feedback is disrupted
when C1C2 = 00; the feedback output Q resets to 0 which makes the reversible
D latch testable with all 0s test vector for any stuck-at-1 fault. Similarly, when
C1C2 = 11 the output Q sets to 1 and the design becomes testable with all 1s
test vector for any stuck-at-0 fault. Thus, the proposed reversible D latch design
with asynchronous set/reset significantly reduces the testing cost. Thus if we
design asynchronous set/reset D latch only with Fredkin gates we can have the
significant testing benefits.