Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 142

the negative enable reversible D latch can be mapped to the 2nd output of the
Fredkin gate as shown in Fig. 8 (a). The second Fredkin gate in the design take
cares of the fanout. The second Fredkin gate in the design also makes the design
testable by two test vectors all 0s and all 1s by breaking the feedback based on
control signals C1 and C2, as illustrated above for positive enable reversible D
latch. The working of the testable negative enable reversible D latch in normal
mode is illustrated in Fig. 8 (b). The negative enable D latch is helpful in the
design of testable reversible master-slave flip-flops. This is because it can work
as a slave latch in the testable reversible master-slave flip-flops in which no clock
inversion is required. The details of which are discussed in the section describing
reversible master-slave flip-flops.
(a) Fredkin gate based T latch with control signals C1, C2 and C3, where
C3 helps in realizing the AND function while C1 and C2 operates the test
mode as well as the normal mode
(b) Fredkin gate based T latch in normal mode: C1=0 and C2=1
(c) Fredkin gate based T Latch in test mode for detecting any stuck-at-0
fault: C1=1 and C2=1
(d) Fredkin gate based T Latch in test mode for detecting any stuck-at-1
fault: C1=0 and C2=0
Fig. 9. Design of testable reversible T Latch using conservative Fredkin gate