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(a) Design of testable Fredkin gate based asynchronous set/reset
D Latch with fanout
(b) Design of testable Fredkin gate based reversible asynchronous
set/reset D latch without fanout. For C1C2=01, the asynchronous
set/reset D latch operates in normal mode. For C1C2=00, the asyn-
chronous set/reset D latch operates in test mode for detecting any
stuck-at-1 faults. For C1C2=11, the asynchronous set/reset D latch
operates in test mode for detecting any stuck-at-0 faults.
Fig. 10. Design of testable reversible asynchronous set/reset D latch
4 Design of Testable Master-Slave Flip-Flops
In the existing literature, the master-slave strategy of using one latch as a master
and the other latch as a slave is used to design the reversible flip-flops [ 11 , 57 ,
68 , 69 ]. In this work, we have proposed the design of testable flip-flops using the
master-slave strategy that can be detected for any stuck-at faults using only two
test vectors all 0s and all 1s. Figure 11 (a) shows the design of the master-slave
D flip-flop in which we have used positive enable Fredkin gate based testable D
latch shown in Fig. 7 (b) as the master latch, while the slave latch is designed
from the negative enable Fredkin gate based testable D latch shown earlier in
Fig. 8 (a). The testable reversible D flip-flops has four control signals mC1, mC2,
sC1 and sC2. mC1 and mC2 control the modes for the master latch, while sC1
and sC2 control the modes for the slave latch. In the normal mode, when the
design is working as a master-slave flip-flop the values of the control signals will
be mC1 = 0 and mC2 = 1, sC1 = 0 and sC2 = 1 (similar to values of the control
signals C1 and C2 earlier described for the testable D latches).
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