Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 141

of the reversible D latch using the Fredkin gate. But fan-out is not allowed
in conservative reversible logic. Moreover, the design cannot be tested by two
input vectors all 0s and all 1s because of feedback, as the output Q would latch
1 when the inputs are toggled from all 1s to all 0s and could be misinterpreted
as stuck-at-1 fault.
In this work, we propose to cascade another Fredkin gate to output Q as
shown in Fig. 7 (b). The design has two control signals, C1 and C2. The design
can work in two modes: (a) normal mode; (b) test mode. Normal Mode :The
normal mode is shown in Fig. 7 (c) in which we will have C1C2 = 01 and the
design will work as a D latch without any fanout problem. Test Mode (Disrupt
the Feedback) : In test mode , when C1C2 = 00 as shown in Fig. 7 (d) the design
will be testable with all 0s input vectors, as output T1 will become 0 resulting
in the testable design with all 0s input vectors. Thus any stuck-at-1 fault can
be detected. When C1C2 = 11 as shown in Fig. 7 (e) the output T1 will become
1 and the design will become testable with all 1s input vectors for any stuck-
at-0 fault. It can seen from the illustration that C1 and C2 will disrupt the
feedback in test mode, and in normal mode will take care of the fan-out. Thus
our proposed design works as a reversible D latch and can be tested with only
two test vectors, all 0s and all 1s, for any stuck-at fault by utilizing the inherent
property of conservative reversible logic.

(a) Fredkin gate based negative enable D latch with
control signals C1 and C2

(b) Fredkin gate based negative enable D latch in nor-
mal mode

Fig. 8. Design of testable negative enable D latch using conservative Fredkin gate

3.1 Design of Testable Negative Enable Reversible D Latch

A negative enable reversible D latch will pass the input D to the output Q when
E = 0; otherwise maintains the same state. The characteristic equation of the
negative enable D latch is

¯

Q

+ =

D · E E · Q

+ . This characteristic equation of