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(a) Fredkin gate based
D latch
(b) Fredkin gate based D latch with control signals C1
and C2
(c) Fredkin gate based D Latch in normal mode: C1=0
and C2=1
(d) Fredkin gate based D latch in test mode for stuck-
at-0 fault : C1=1 and C2=1
(e) Fredkin gate based D latch in test mode for stuck-
at-1 fault: C1=0 and C2=0
Fig. 7.
Design of testable reversible D latch using conservative Fredkin gate
3 Design of Testable Reversible Latches
+
¯
+
=
The characteristic equation of the D latch can be written as
.
In the proposed work, E (Enable) refers to the clock and is used interchangeably
in place of clock. When the enable signal (clock) is 1, the value of the input D is
reflected at the output that is
Q
D ·E
E ·Q
Q
+
= D. While, when E = 0 the latch maintains
+
= Q. The reversible Fredkin gate has two of
its outputs working as 2:1 MUxes, thus the characteristic equation of the D
latch can be mapped to the Fredkin gate (F). Figure
7
(a) shows the realization
Q
its previous state, that is
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