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21. Brayton,
R.K.,
McMullen,
C.,
Hachtel,
G.D.,
Sangiovanni-Vincentelli,
A.:
Logic
Minimization Algorithms for VLSI Synthesis. Kluwer, Norwell (1984)
22. Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, R.,
Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.: SIS: a system for sequential
circuit synthesis. Technical Report, University of California, Berkeley (1992)
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