Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 131

Reversible Logic Based Design and Test
of Field Coupled Nanocomputing Circuits

B

Himanshu Thapliyal (

) , Nagarajan Ranganathan, and Saurabh Kotiyal

Department of Computer Science and Engineering,
University of South Florida, Tampa, FL, USA
{ hthapliy,ranganathan } @cse.usf.edu, [e-mail]

Abstract. Reversible computing is based on logic circuits that can gen-
erate unique output vector from each input vector, and vice versa, that
is, there is a one-to-one mapping between the input and the output vec-
tors. Reversible computing is the only solution for non-dissipative ultra
low power green computing. Conservative reversible circuits are a spe-
cific type of reversible circuits, in which there would be an equal number
of 1s in the outputs as there would be on the inputs, in addition to
one-to-one mapping. This work illustrates the application of reversible
logic towards testing of faults in traditional and reversible field coupled
nanocircuits (Portions of this chapter are based on [ 2 ]. The enhancement
is comprehensive treatment of: basics of reversible computing, motiva-
tion for reversible computing, background on conservative logic, basics of
QCA computing, such as QCA logic devices and QCA clocking, related
work etc. Several new reversible testable designs are introduced such
as design of testable reversible T latch, design of testable asynchro-
nous set/reset D latch and master-slave D flip-flop, design of testable
reversible complex sequential circuits. QCA layouts of conservative logic
gates are introduced with internal design details of QCA logic devices.
Complete fault patterns information and analysis are provided for conser-
vative logic gates. The synthesis of non-reversible testable design based
on MX-cqca gate is extended to MX-cqca based implementation of stan-
dard functions. The significance of this work and broader prospective for
future directions is also presented.). We propose the design of two vec-
tors testable sequential circuits based on conservative logic gates. The
proposed sequential circuits based on conservative logic gates outper-
form the sequential circuits implemented in classical gates in terms of
testability. Any sequential circuit based on conservative logic gates can
be tested for classical unidirectional stuck-at faults using only two test
vectors. The two test vectors are all 1s, and all 0s. The designs of two
vector testable latches, master-slave flip-flops, double edge triggered flip-
flops, asynchronous set/reset D latch and D flip-flop are presented. The
importance of the proposed work lies in the fact that it provides the
design of reversible sequential circuits completely testable for any stuck-
at fault by only two test vectors, thereby eliminating the need for any
type of scan-path access to internal memory cells. The reversible designs
of the double edge triggered flip-flop, ring counter and Johnson Counter
are proposed for the first time in literature. We are showing the appli-
cation of the proposed approach towards 100 % fault coverage for single