Graphics Reference
In-Depth Information
computing architectures can be found in [
33
]. In this chapter, we will consider a sim-
ple computing architecture based entirely on low-cost FPGAs that, in our opinion,
represent an optimal solution to design compact, low-cost, low-power 3D sensors
based on stereo vision.
5.2.1 Field-Programmable Gate Arrays
FPGAs can be configured, and in most cases reconfigured many times, by means
of hardware description languages (HDLs) such as VHDL or Verilog. The inter-
nal structure of an FPGA consists of a large amount of
logic cells
, each contain-
ing a small amount of elementary logic blocks (e.g., Flip-Flops, multiplexers, and
lookup tables). Distributed into the FPGA, there are also small multiport memories,
often referred to as
block RAM
, with fast access time. Moreover, modern low-cost
FPGAs often integrate configurable DSPs for efficient arithmetic operations, clock
managers, and high-speed transceivers. All these components can be configured by
programmers/designers according to their specific requirements by means of HDLs.
For instance, considering a Xilinx Spartan 6 Model 45 FPGA, we can find roughly
44,000 logic cells, 116 dual-port block RAMs (18Kb each), 58 DSPs, 4 clock man-
agers, and 358 configurable I/O pins. It is worth noting that the reconfigurable logic
of an FPGA can be configured/programmed with HDLs at a higher level of abstrac-
tion using a
behavioral
programming methodology. However, mapping computer
vision algorithms on the reconfigurable logic with HDLs is not as simple as mapping
the same algorithms on CPUs with traditional high-level programming languages.
Nevertheless, recent years have seen the appearance of effective high-level synthe-
sis (HLS) tools that enable the automatic conversion of code written in a standard
programming language, such as C/C++ or Matlab, into HDLs. Despite these facts,
being the hardware resources of the reconfigurable logic highly constrained, a clear
understanding of the overall FPGA architecture and of the available resources is
crucial for writing optimized code with HDLs as well as with HLS tools. The key
advantage, compared to most other computing architectures, is that FPGAs, thanks
to their complete reconfigurability, can be programmed to massively exploit paral-
lelism and tailored to specific application requirements enabling one to obtain the
optimal performance/Watt.
5.2.2 Stereo Vision
Stereo vision [
31
] is a technique aimed at inferring dense or sparse depth maps from
two or more views of the same scene observed by two or more cameras. Although
increasing the number of cameras has the potential to improve accuracy and reliabil-
ity, the binocular setup (i.e., deploying two imaging sensors) is frequently deployed
in practice. Due to the many applications that can take advantage of dense depth data,
