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this topic has received a constant research interest in the last decades, and significant
algorithmic improvements have been proposed [
15
,
31
]. However, most dense stereo
vision algorithms are computationally demanding, and parallel computing architec-
tures are in most cases mandatory if one is to obtain dense depth measurements in
real time. Not surprisingly, for this reason, FPGAs have attracted the interest of many
researchers working in this field [
33
].
5.3 Overview of the Constrained Computing Architecture
Our target computing architecture is aimed at minimizing cost, power consumption,
and at enabling better portability with respect to future evolutions of the FPGA core
that, in our case, currently relies on the Xilinx Spartan 6 family. The design strategy
adopted here would easily enable the porting of algorithms to FPGA devices pro-
vided by different manufacturer to high-end devices manufactured by Xilinx, such
as devices belonging to the high-end Virtex class as well as to new computing archi-
tecture made of multicore and programmable logic such as those recently proposed
by Altera or Xilinx (e.g., the Zynq platform for Xilinx). In particular, these latter
hybrid
architectures, made of ARM cores tightly coupled with powerful reconfig-
urable logic, would perfectlymatch our strategy enabling the design of self-contained
smart cameras with a very simplified and almost standard hardware design.
A brief overview of our current computing architecture is depicted in Fig.
5.2
.It
is based on a single FPGA and aims to obtain dense depth maps at more than 30+ fps
processingWVGA (752
480) stereo pairs sensed by monochrome or color sensors.
These specific imaging sensors, manufactured by Aptina (specifically the MT9V034
model adopted for our evaluation), provide some interesting features well suited to
smart cameras for computer vision applications. In fact, these imaging sensors have
global shutter capability, are available in monochrome or color (based on the Bayer
pattern) format, have a maximum frame rate of 60 fps, provide an optional LVDS
data communication between sensors and the device (the FPGA in our case) that
manages the video streams and also enable simultaneous acquisition by means of
hardware synchronization. Nevertheless, it is worth pointing out that our design is
not constrained to this specific imaging sensor and other devices could be used in
place with minimal modifications to the overall design. Observing Fig.
5.2
, we can
notice that the two synchronized color or monochrome imaging sensors are con-
nected, through two
low-voltage differential signaling
(LVDS) channels for clocks
and data, to the FPGA. This choice, plus the additional LVDS link between the two
imaging sensors, enables us to put the sensors and the computing platform in arbi-
trary positions, even at distances of meters, in order to deal with different setups
according to different application requirements. For instance, in gesture recognition
applications, the baseline is typically very small (few centimeters), while for systems
aimed at autonomous navigation, the baseline can be significantly larger (50 cm or
more). Both cases would be easily handled by the depicted solution. Despite this
important fact, other crucial design goals in our project were minimal power require-
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