Hardware Implementation of Embedded Fuzzy Controllers on FPGAs and ASICs - Fuzzy Modeling and Control: Theory and Applications - page 239

Table 13.5 Number of (Slices / RAM Blocks / Multipliers) for function F 2 versus implementation
option and defuzzification method
Method

XSG A_ROM_ROM A_LB_LB M_ROM_ROM M_LB_LB

FM (200/1/4) (202 / 0 / 4) (216/0/4) (128 / 4 / 2) (1156 / 0 / 2)

FMs (152/1/4) (136 / 0 / 4) (151/0/4) (60 / 4 / 2) (1096 / 0 / 2)

WFM (203/2/6) (266 / 0 / 6) (273/0/6) (193 / 4 / 4) (1218 / 0 / 4)

TS1 (259/3/7) (282 / 0 / 7) (326/0/7) (209 / 4 / 5) (1268 / 0 / 5)

TS1s (214/3/7) (206 / 0 / 7) (250/0/7) (131 / 4 / 5) (1190 / 0 / 5)

Table 13.6 Number of (Slices / RAM Blocks / Multipliers) for function F 3 versus implementation
option and number of bits
N. Bits XSG A_ROM_ROM A_LB_LB M_ROM_ROM M_LB_LB

6 (153/2/5) (156 / 0 / 5) (146/0/5) (106/2/3) (164 / 0 / 3)

8 (183/2/5) (199 / 0 / 5) (181/0/5) (139/2/3) (393 / 0 / 3)

10 (203/2/6) (261 / 0 / 6) (238/0/6) (189/4/4) (927 / 0 / 4)

12 (233/2/6) (302 / 0 / 6) (273/0/6) (222 / 14 / 4) (1972 / 0 / 4)

synthesis tool used in this work (xst) is able to identify RAM or ROM memories
in the first stage of the synthesis process. However, due to optimization motives,
these elements are never implemented by means of BRAM block. For this reason,
data in columns 3 and 4 are similar for all the considered cases. Comparing both
implementation techniques, the number of slices is more or less equivalent, but
XSG-based designs require BRAM blocks.
Regarding VHDL-based designs employing memory-based antecedents, ROM
implementations allow reducing the number of slices, but they increase the amount
of required BRAM blocks (column 5 in tables). This drawback can be solved by
implementing antecedent and rule memories by means of logic blocks. However the
number of required slices grows in this case when the number of inputs or the bit
size is incremented, thus implying much higher resource consumption than the other
cases (column 6 in tables).

13.6 Design Example

In order to demonstrate the utility of the proposed design flow, the hardware imple-
mentation of different fuzzy controllers for the well-known problem of double inte-
grator is described in this Section. Four cases have been considered. The first three
correspond to 2-input 1-output fuzzy systems using different defuzzification meth-
ods. The fourth fuzzy controller is inspired by the two-level hierarchical implemen-
tation proposed in Baturone et al. ( 2011 ). Control surfaces provided by hardware