Hardware Implementation of Embedded Fuzzy Controllers on FPGAs and ASICs - Fuzzy Modeling and Control: Theory and Applications - page 238

Table 13.2 MSE for approximation of function F 2 versus implementation option and defuzzifica-
tion method
Method SysGen

A_ROM_ROM A_LB_LB M_ROM_ROM M_LB_LB

10 − 4 10 − 4 10 − 4 10 − 3 10 − 3

FM 1 . 0360 × 9 . 6856 × 9 . 6856 × 1 . 0176 × 1 . 0176 ×

10 − 4 10 − 4 10 − 4 10 − 4 10 − 4

FMs 4 . 4414 × 4 . 1606 × 4 . 1606 × 8 . 9646 × 8 . 9646 ×

WFM 9 . 1823 × 10 − 4 8 . 0195 × 10 − 4 8 . 0195 × 10 − 4 8 . 4375 × 10 − 4 8 . 4375 × 10 − 4

10 − 4 10 − 3 10 − 3 10 − 3 10 − 3

TS1 8 . 2597 × 2 . 2031 × 2 . 2031 × 2 . 2432 × 2 . 2432 ×

10 − 4
FM Fuzzy Mean; WFM Weighted Fuzzy Mean; TS1 first-order Takagi-Sugeno; FMs and TS1s,
FM and TS1 not requiring the final division stage

10 − 4 10 − 4 10 − 4 10 − 4 TS1s 1 . 7448 × 3 . 0961 × 3 . 0961 × 3 . 5226 × 3 . 2723 ×

Table 13.3 MSE for approximation of function F 3 versus implementation option and number of
bits
N. Bits XSG A_ROM_ROM A_LB_LB M_ROM_ROM M_LB_LB

10 − 2 10 − 3 10 − 3 10 − 4 10 − 4

6 3 . 8114 × 1 . 3643 × 1 . 3643 × 3 . 4146 × 3 . 4146 ×

10 − 3 10 − 4 10 − 4 10 − 4 10 − 4 8 2 . 0894 × 1 . 5878 × 1 . 5878 × 1 . 2279 × 1 . 2279 ×

8 . 0650 × 10 − 4 1 . 1098 × 10 − 4 1 . 1098 × 10 − 4 1 . 0973 × 10 − 4 1 . 0973 × 10 − 4 10

10 − 4 10 − 4 10 − 4 10 − 4 10 − 4 12 6 . 8587 × 1 . 0905 × 1 . 0905 × 1 . 0969 × 1 . 0969 ×

10 − 4 10 − 4 10 − 4 10 − 4 10 − 4 14 6 . 8059 × 1 . 0778 × 1 . 0778 × 1 . 0796 × 1 . 0796 ×

Table 13.4 Number of (Slices/RAM Blocks/Multipliers) for function F 1 versus implementation
option and number of labels
N. Labels XSG A_ROM_ROM A_LB_LB M_ROM_ROM M_LB_LB

3 (187/1/3) (168/0/3) (168 / 0 / 3) (99/4/1) (152 / 0 / 1)

5 (200/1/3) (185/0/3) (173 / 0 / 3) (118/4/1) (160 / 0 / 1)

7 (200/1/3) (193/0/3) (186 / 0 / 3) (122/4/1) (208 / 0 / 1)

9 (207/1/3) (230/0/3) (226 / 0 / 3) (161/4/1) (202 / 0 / 1)

13.5.2 Results in Terms of Resource Consumption

Resources required for implementing on a Spartan-3A FPGA the fuzzy controllers
designed with xfsg and xfvhdl are presented in Table 13.4 (for different number
of labels), Table 13.5 (for different defuzzification methods), and Table 13.6 (for
different bit size). Entries in tables show the total number of slices, the amount of
BRAM blocks, and the number of built-in multipliers used in each case.
As can be observed in the tables, the required resources grow with the number
of labels, the bit size, and the number of parameters employed by defuzzification
methods. XSG-based designs (column 2 in tables) employ arithmetic MFCs and
implement the rule memories by using BRAM blocks. In the case of VHDL-based
design, the user can select both the kind of memory (ROM, RAM, and logic blocks)
and the FPGA implementation (block or distributed) of these elements. The Xilinx's