Selected Topics in Applied Signal Processing - Digital Signal Processing: An Introduction with MATLAB and Applications - page 151

Fig. 3.16 Locking region of
the 1st-order SDPLL

3

2

R

1

1 2

ω o / ω

Frequency ratio, W =

Phase Plane Diagram

Phase plane diagrams represent the phase at the (k ? 1)th sampling instant, /
(k ? 1), as a function of the phase at the kth sampling instant, /(k). Such diagrams
are useful for studying the convergence behavior of the SDPLL.
For the first-order SDPLL, the system equation is given by (see Eq. 3.33 ):

/ ð k þ 1 Þ¼ / ð k Þ K 2 sin ½ / ð k Þ þ K o :

If one puts x = /(k) and y = /(k ? 1), one gets the following simple equation:

y ¼ g ð x Þ¼ x K 2 sin ð x Þþ K o :

If one assigns a value for / (0), then successive phase errors {/ (k)|k = 1? ? }
can be found and plotted (modulo 2p) by successive projections on the curves
y = x and y = g(x). This is shown in Fig. 3.17 for h o = 2.5 rad, t o = 0,
K 1 = 1.7, center frequency f o = 1 Hz, and input frequency f i = 0.83 Hz (hence
W = 1.2). The locking point is a point of intersection between the two curves.
Note that the values of W and K 1 are inside the locking region R. Figure 3.17
also shows the sampling process with the phase error process for the same
parameters. Figure 3.18 depicts the frequency tracking process under the above
circumstances.

SDPLL in Noise

Figure 3.19 shows the frequency tracking probability density function for the same
circuit parameters as above in the presence of AWGN noise. It is seen that the pdf
(f) has a maximum at approximately f = f i . Hence, the SDPLL can detect the input
frequency in the presence of noise, even for low SNRs. Figure 3.20 shows the
variance of this frequency estimate as a function of the SNR. As expected, it
decreases when SNR increases.