Digital Signal Processing Reference
In-Depth Information
π
φ
(1)
−
π
π
φ
(0)
φ
ss
φ
(3)
φ
(2)
−
π
φ
(
k
), rad
t
(0)
t
(1)
t
(2)
t
(3)
T
(1)
T
(2)
T
(3)
←→
←→
←→
t
, sec
0
1
2
t
(0)
t
(1)
t
(2)
t
(3)
π
1
2
t
, sec
0
−
π
Fig. 3.17 Locking process of the 1st-order SDPLL for h
o
= 2.5 rad, t
o
= 0, K
1
= 1.7,
f
o
= 1 Hz, and f
i
= 0.83 Hz (hence W = 1.2). Above phase plane diagram. Middle sampling
process. Below phase error process
Fig. 3.18 Frequency track-
ing process using the
1st-order SDPLL with
h
o
= 2.5 rad, t
o
= 0,
K
1
= 1.7, f
o
= 1 Hz, and
f
i
= 0.83 Hz (hence
W = 1.2)
t
(0)
t
(1)
t
(2)
t
(3)
1
t
, sec
0
1
2
3.4.2.4 The Second-Order Noise-Free SDPLL
The first-order SDPLL locks on a non-zero steady-state phase error /
ss
¼
sin
1
ð
K
o
=
K
2
Þ:
This can be an unwanted characteristic when the PLL is used for syn-
chronization. In such a case the second-order loop may be necessary as it locks on
zero phase error. The second-order SDPLL utilizes a proportional and an accu-
mulation path digital filter:
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