Selected Topics in Applied Signal Processing - Digital Signal Processing: An Introduction with MATLAB and Applications - page 150

Using Eqs. 3.28 and 3.31 gives the following difference equation:

/ ð k þ 1 Þ¼ / ð k Þ K 2 sin ½ / ð k Þ þ K o ð 3 : 33 Þ

where K o ¼ 2p ð x x o Þ= x o and K 2 = x G 1 A.IfK 1 is defined to be K 1 = x o G 1 A,
and W is defined as the frequency ratio W = x o /x, then K 2 = K 1 (x/x o ) =
K 1 /W. The parameters W and K 1 control the system operation range as discussed
below.

Locking Conditions

If locking occurs, then /(k ? 1) = /(k) = / ss (/ ss being the steady-state phase
error). Using Eq. 3.33 it follows that:

K o ¼ K 2 sin ð / ss Þ) / ss ¼ sin 1 ð K o = K 2 Þ ð 3 : 34 Þ

) K o = K 2 j j \1 ð 3 : 35 Þ

Equation 3.35 leads to the following condition (prove as an exercise!):

K 1 [ 2p 1 W j j ð 3 : 36 Þ

Now the theory of Fixed Point Analysis states that the equation g(w) = w has a
solution w * only if the following condition is satisfied (see [ 6 ]):

g 0 ð w Þ

j j \1 ð 3 : 37 Þ

Hence, Eq. 3.33 has a solution as in Eq. 3.31 only if:

j 1 K 2 cos ð / ss Þ j \1

q

K 2 K o ) 1 \1

) K 2 K o \4

which gives the following condition:
K 1 \

p

ð 4 þ 4p 2 Þ W 2 8p 2 W þ 4p 2 ð 3 : 38 Þ

Equations 3.35 and 3.38 specify the frequency locking region of the 1st-order
SDPLL as illustrated in Fig. 3.16 . Hence, if the frequency of the incoming signal is
such that x = x o ¼ 1 = W 2 R, where R is the region of locking in the (W,K 1 ) plane,
then the SDPLL is capable of tracking this frequency. It is then also capable of
eventually locking on the input phase. Note that as K 1 approaches 2, the locking
range becomes wider. Practically, locking occurs when j / ð k þ 1 Þ / ð k Þj \ ,
where e is a small positive number.