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A Appendix
In this section we explain the circuit details of Flexicache for a sub-array and for the
address decoder that we used in the evaluation of energy and area overhead. In the
main text, we present abstract views of these structures for simplicity.
A.1 Details of Sub-array
Figure 8 shows the block diagram of each sub-array structure. The figure presents the
necessary buffers, comparators, parity calculators and control and data lines in detail.
