The Architecture of Electronic Data Carriers - RFID: Fundamentals and Applications in Contactless Smart Cards and Identification - page 288

Chip

EEPROM

Common
EEPROM

MIFARE ®
interface
and logic

Inter-
face

CPU

Access
configuration matrix

RAM ROM

Sector access
µ C proprietary

MIFARE ® proprietary
common use for C and MIFARE ® µ

Figure 10.28 Block diagram of the MIFARE -plus 'dual interface card' chip. In contactless
operating mode the common EEPROM is accessed via a MIFARE -compatible state machine.
When operating via the contact interface a microprocessor with its own operating system accesses
the same memory (reproduced by permission of SLE 44R42, Infineon AG, Munich)

in which the arrangement of the individual segments and memory blocks are identical
to that of a conventional MIFARE card (see Section 10.1.3.5).
The contact interface, on the other hand, is based upon a microprocessor with its
own smart card operating system . The above-mentioned memory segmentation is once
again present when the microprocessor accesses the common EEPROM. The operating
system can therefore only read and write the common EEPROM in blocks within the
corresponding sectors.
In addition, the write and read rights for individual memory blocks of the common
EEPROM can be configured separately for the contactless and contact interface. These
access rights are set in, and monitored by, the Access Configuration Matrix. This also
facilitates the realisation of hierarchical security concepts.

10.2.1.2 Modern concepts for thedual interface card

Figure 10.29 shows the block diagram of a modern dual interface card. This card is
based upon a 8051 microprocessor with a smart card operating system . The contactless
interface is formed by a CIU ( contactless interface unit ), which can be configured by
the CPU via register addresses or can also facilitate a status interrogation of the CIU.
A modern CIU automatically performs the transfer of a data block from and to a
reader and thereby automatically performs the necessary coding or decoding of the
data stream according to the specifications in the standard ISO/I EC14443-2 and ISO/I
EC14443-3. Often it also performs the automatic calculation and verification of the
transmitted CRCs.
To send a data block, the operating system only needs to store the data block to be
sent in the RAM memory of the chip and load the corresponding memory address and
block length into the configuration register of the CIU. The CPU is no longer actively
involved in the initiated data transfer and can thus be switched into power down mode