The Architecture of Electronic Data Carriers - RFID: Fundamentals and Applications in Contactless Smart Cards and Identification - page 289

LA RF

interface

UART
ISO14443

3DES
co-processor

RAM EEPROM

PKI
co-processor

Card coil

LB Security

sensors

Power on
reset

MMU
memory
management
unit

IO2

Ultra low power
80C51
compatible core

CRC
generator

Interrupt
system

IO3

Voltage
regulator

Clock
input filter

TIMER0
16 Bit
TIMER1
16 Bit

Programmable
IO
1, 2, 3

User-rom
Test-rom

UART
ISO 7816

Reset
generator

ISO
contacts

MGa 12/01

Figure 10.29 Block diagram of the dual interface card chip 'MIFARE ProX' (reproduced by
permission of Philips Semiconductors Gratkorn, A-Gratkorn)

( power saving mode ) for the duration of the data transfer (Muhlbauer, 2001). When a
data block is received, the data from the CIU is then automatically stored in the chip's
RAM and the CRC of the received block is verified.
Short transaction times represent a particularly important requirement for contact-
less applications. For ticketing applications a maximum transaction time of 100ms
is a generally accepted value. In order to facilitate the calculation of cryptographic
functions within this short time interval, many dual interface chips have cryptographic
coprocessors . In banking applications, symmetrical encryption algorithms such as DES
(data encryption standard) and triple DES are normally used (Figure 10.30). Encryption

Encryption sequence

Plain data
'Hello world'

DES
encryption

DES
decryption

DES
encryption

Cipher data
0x2A, 0xFA,...

Key A Key B Key A

Cipher data
0x2A, 0xFA,...

DES
decryption

DES
encryption

DES
decryption

Plain data
'Hello world'

Decryption sequence

Figure 10.30 Calculation of the 3DES (triple DES). Encryption (above) and decryption (below)
of a data block (reproduced by permission of Philips Semiconductors Gratkorn, A-Gratkorn)