Long-Term Memory Neural Circuits, Fast and Precise - Brain Theory from a Circuits and Systems Perspective - page 131

Table 8.3 Boolean truth
table for a standard cell

Rin x Q Rout

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

Fig. 8.2 Rout-Rin logic

In Boolean algebraic terms False is 0; True is 1. The first entry means that if
there is no bus signal coming from the left (Rin ¼ 0), then none is transmitted to the

right (Rout 0). This keeps a memory word dormant until needed. The second

entry in the table means that if there is no cue (x

¼

¼ 0) then there is no change in

Rout and Rout ¼ Rin ¼ 1. The third entry means that if there is a cue for an

attribute, or x ¼ 1, but there is no memory of this feature in this word, or Q ¼ 0,

then bus operations terminate (Rout ¼ 0). The fourth entry means that if there is a

cue for an attribute (x ¼ 1) and if there is also a memory of this attribute (Q ¼ 1)

then there is no change in Rout, and Rout ¼ Rin ¼ 1. A proper binary “truth” table

can now be constructed (Table 8.3 ).
In this table, entries 1-4 express condition 1, no input (Rin ¼ 0) gives no output

(Rout 0). Entries 5, 6 express condition 2, no cue permits an output, with or

without memory. It permits a recovery of attributes that are not covered by the cues.
Entry 7 shows condition 3, cue but no memory gives no output, which will prevent a
return from this word. Entry 8 shows condition 4, both cue and a memory of the
attribute represented by the cue give an output.
The appropriate Boolean equation for Rout, derived from the truth table using
standard symbols (￿, +, 0 for AND, OR, NOT) is

¼

x 0 þ

Rout ¼ Rin ½ Q :

x 0 represents a NOT function of x. A logic circuit corresponding to this equation
appears in Fig. 8.2 .
This can be implemented using neurons. A similar neural logic circuit may be
written for Lout in terms of Lin (not shown).