Long-Term Memory Neural Circuits, Fast and Precise - Brain Theory from a Circuits and Systems Perspective - page 130

Fig. 8.1 Standard memory
cell for biological memory
modeling

Table 8.1 Definition
of memory cell signals

Q Memory signal from memory neuron

x Cue for given feature (input)

x o ¼ x Cue to cells below (output)

y Memory from cells below (input)

y o ¼ y Memory of a given feature (output)

Rin Right-going local bus signal (input)

Rout Right-going local bus signal (output)

Lin Left-going local bus signal (input)

Lout Left-going local bus signal (output)

Table 8.2 Desired logic
for standard cell

Conditions Rout

1 Rin False

x either True or False
Q either True or False

¼ Rout ¼ Rin ¼ False

2 Rin ¼ True Rout ¼ True

x False, no feature

Q either True or False

¼

3 Rin ¼ True Rout ¼ False

x ¼ True

Q ¼ False

4 Rin True

x ¼ True
Q ¼ True

¼ Rout ¼ True

element of long-term memory. An enable signal E, not shown, is available to
activate cells and memory elements as needed.
A standard memory cell may be synthesized based on input and output behavior
as defined below. Signals are defined as in Table 8.1 .
Note that neurons sometimes work in pairs: Cue signals from a cue editor
system, the x signals, travel down. Recalled features, the y signals, travel up and
into a recall referee system. Memory word bus signals also work in pairs: A right-
going bus signal travels to the right, from Rin to Rout along a local bus. A left-going
bus signal travels to the left, from Lin to Lout. Rin and Lin are going to be energized
by outside enable signals. The desired logic has a truth table (Table 8.2 ).