Plans for a Recall Referee - Brain Theory from a Circuits and Systems Perspective - page 101

Circuits That Support a Recall Referee
Attribute Registers
Attribute registers are similar to the qubit registers for cues described under cue
editor. When they receive a Load command they record what is applied to their
inputs. A load command is required whenever a new Hit signal arrives from long-
term memory. Returns are expected to occur at regular intervals as a group.
Asynchronous Decoding
Hit signals arrive in groups in an approximately periodic fashion. In this case it is
possible to direct returns into respective registers.
The first Hit signal is converted into a single pulse as in the top of Fig. 6.2 . After
the first hit a short-term memory neuron (STM1) provides an exact number of
pulses to stop subsequent Hit pulses beyond the first. The number of STM1 pulses
must be one less than the number of Hit pulses (or STM1 can be removed if there is
only one Hit pulse for each group of returns). This assures that only one pulse is in
Fig. 6.2 Generation
of load commands