Digital Signal Processing Reference
In-Depth Information
selected video resolution, although in example of free running
they will use as much bandwidth as available
possibly locking
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out lower-priority masters from the memory.
A processor master does not normally have a bandwidth
limit
it will use as much bandwidth as is available and can be
consumed. Most processors are only able to pipeline a limited
number of memory accesses, so the latency of the memory can
limit the amount of bandwidth they can consume. Processors are
normally put at the lowest priority to prevent them from starving
video masters, which have a bandwidth target.
Many arbiters, including the Altera external memory inter-
face toolkit, have an optional efficiency monitoring feature
which collects statistics about the bandwidths and latencies
used by different masters. This efficiency monitor can be used
to check that the memory is running at a sufficiently high
overall bandwidth, and can help with optimization when it is
not.
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21.10 Check Data Within Stream
During the prototype stage all components have bugs that
must be fixed. The usual hardware flow is to fix these bugs
through simulation where the visibility into the system is good.
This is harder for video components as the high data rates
mean that complex components can take several minutes to
simulate each frame. For edge-case bugs, which occur once every
few hours on video data, this would mean many days of simu-
lation before a bug occurs. These bugs are only really debuggable
in hardware.
Most debug components, including the Altera trace system,
can be set up to continuously capture data into a circular buffer.
When the trace system is
triggered
it stops capturing data,
sending its stored data to the host for analysis. Ignoring the
activity of the system significantly before the trigger lets you
concentrate on the immediate causes of the bug, rather than
having to wade through large amounts of captured data.
What drives the trigger signal? For hard-to-find bugs you
might write custom hardware, which monitors various parts of
the system and sends a trigger when misbehavior is detected. This
is difficult, can be error-prone and is not always necessary.
Most component vendors ship bus protocol monitors that are
used in simulation to check that the signals on a bus do not
violate the specification. For example, a lot of memory-mapped
buses require that after an access has started the address signals
must remain stable until that access is accepted by the slave. A
