Digital Signal Processing Reference
In-Depth Information
control statistics will report that there is no backpressure or
unavailable data
i.e. “ready” and “valid” will be high for most of
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the frame.
The timing information on the captured video packets reports
the average frame rate passing through the monitor. If the
streaming video interface is free running then the frame rate in
parts of the video pipeline will be much faster than expected.
21.9 Insuf
cient Memory Bandwidth
Some video processing components, such as a color space
converter, can process the video data one pixel at a time. Others
need to store the pixels between input and output
the simplest
examples are the buffer components that write the input pixels to
a frame buffer in memory and read from memory (with different
timing) to create the output pixel stream.
Components using a frame buffer demand a large amount of
memory bandwidth
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the sum of the bandwidth of the input and
output data rates. If the memory subsystem is not designed
correctly then it will not be able to provide this bandwidth. This
will cause excessive flow control of the input and/or output which
in turn will make FIFOs in other components overflow or
underflow as described previously.
Because of their size, most frame buffers are stored in external
memory, which is usually shared between multiple, different,
memory-mapped masters. Even in the case where memory is not
shared, a double- or triple-buffer component has two masters,
one to write and the other to read.
When there are multiple masters for the same memory-
mapped slave, an arbiter is needed to share the slave's bandwidth
between the masters. In some cases the arbiter is inserted auto-
matically as part of the bus fabric
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in other cases it is explicitly
inserted by the user as a separate component, or as part of the
slave component.
The Altera multi-port front-end component is a specialized
arbiter which understands the costs of different DDR accesses
and can be configured to maximize bus efficiency. When used
correctly this component can achieve memory-bandwidth effi-
ciency of over 90%
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i.e. the number of cycles lost due to bank
opens, closes, read-after-write delays and other DDR perfor-
mance hazards is less than 10%.
Setting up the arbiter to achieve high efficiencies is sometimes
complex, as the interface priorities need to be set correctly so that
low-latency masters are serviced quickly. Most video component
masters will use only as much bandwidth as is needed for the
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