Digital Signal Processing Reference
In-Depth Information
21
DEBUGGING FPGA-BASED
VIDEO SYSTEMS
Andrew Draper, Altera video engineering
CHAPTER OUTLINE
21.1 Timing Analysis 201
21.1.1 Check that the Design Meets Timing 202
21.1.2 Fix Your Design if it Does Not Meet Timing
203
21.2 The SystemConsole Debugger 204
21.3 Check That Clocks and Resets are Working
205
21.4 Clocked and Flow Controlled Video Streams
206
21.5 Debugging Tools 206
21.6 Converting from Clocked to Flow-controlled Video Streams
208
21.7 Converting from Flow-controlled to Clocked Video Streams
209
21.8 Free-running Streaming Video Interfaces
210
21.9 Insuf
cient Memory Bandwidth
211
21.10 Check Data Within Stream 212
21.11 Summary
213
In this chapter we will discuss some of the strategies you can
use for debugging a video system built in an FPGA. The examples
use Altera's video debugging tools and methodology, although
the concepts can be applied generally.
Before moving on to the video-specific parts of debugging it is
worth checking that the design has synthesized correctly and has
passed a number of basic sanity checks.
21.1 Timing Analysis
Hardware designs that run from a clock need tomeet a number
of timing constraints. The two most basic of these exist to prevent
errors if a signal changes while it is being sampled by a register:
The input to a register must be stable for a time before the
clock edge on which it is sampled
e
referred to as the
setup
time.
