Digital Signal Processing Reference
In-Depth Information
Table 20.3
The number of bits required to store one line of video
Video frame size
(pixels)
# of pixels ina
line
Color plane/bits
per plane
Sub-
sampling
Video line buffer
(bits)
640
480
640
RGB/8
4:4:4
21
640
1280
72
1280
RGB/8
4:4:4
21
1280
1280
72
1280
YcrCb/8
4:2:2
16
1280
1920
10
1920
YcrCb/10
4:2:2
20
1920
The number of bits required to store one line of video depends
on multiple color space variables as shown in
Table 20.3
.
To minimize the number of memory blocks, it is
extremely important to have the right memory configuration.
Since high-definition is appearing in all facets of the video
market, a line buffer size of 1920 pixels (typical HD resolution
being 1920
1080) must be considered. Each pixel is generally
chroma subsampled at 4:2:2, providing 20 bits per pixel.
The ideal configuration of a memory block when imple-
menting a 1080p HD video line would therefore be 20 bits wide
and 1920 bits (about 2K) deep.
Altera FPGAs have M9K RAMmemory blocks that are designed
to accommodate HD video. Each RAM memory block can be
configured as 2K
4 bits.
Figure 20.6
shows that cascading five of
these blocks in parallel enables a video line-buffer with
a memory-bit efficiency of 93.75% (1920 / 2048) to be easily
implemented.
When selecting FPGAs for HD video processing, the available
configuration options of the embedded memory blocks will
determine the number of video line buffers that can be imple-
mented. A well-planned and flexible block RAM configuration
leads to high bit-efficiency and will allow the design to fit into
a smaller and more economical device.
20.4 Conclusion
When implementing HD video processing designs, memory
resources are generally the more important consideration, given
how memory-intensive video designs are. This chapter gives you
a sense of what to expect both in terms of internal on-chip
memory and also external DDR memory.
