Digital Signal Processing Reference
In-Depth Information
Figure 20.6. Five M9K RAM
memory blocks in parallel.
Which means for this design you need an efficiency of 26.434/
34.133
77.5%. Efficiency in this context is the effect of multiple
masters trying to pull from the memory or write to it. And in some
cases the deinterlacer memory access may be stalled if it is being
used by the frame buffer. This would cause the entire processing
to stall, so the memory subsystem has to be designed such that it
meets the required efficiency.
¼
20.3 Calculating On-Chip Memory
Video scaling will use the most on-chip memory. This calcu-
lation is fairly simple, but depends on the complexity of the
scaling function.
For example, an important part of upsampling and down-
sampling is choosing the appropriate filter kernel. This can help
preserve the sharpness of the edges during interpolation and avoid
aliasing during decimation. Filter response aside, resource usage is
another relevant and often-overlooked aspect of the decision
making process. It is important to realize that aNv
Nhfilter kernel
would translate into Nv
Nh multipliers and Nv line buffers.
Which means that if you choose a 4
þ
4 filter kernel, you will
need enough on-chip memory to store four lines of video. One
video line-buffer stores all the pixels in a single line onto the FPGA
memory. The size and the configuration of this video line buffer
depends upon many factors.
As we have seen before, each pixel is generally represented by
three color planes
RGB, YCrCb, etc. Typically each color plane
in turn is encoded using 8, 10 or even 12 bits. We also have to
factor chroma sub-sampling into our calculations.
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