Digital Signal Processing Reference
In-Depth Information
Setup time
Hold time
Clock
Data
Time
Figure 21.1. Setup and hold times.
The input to a register must remain stable for a time after the
clock edge on which it is sampled
referred to as the
hold time.
Most signals originate from registers in the same clock domain,
the outputs of which change just after the clock edge (i.e. there is
a delay going through the register). There are also delays while the
signals pass through combinational logic, and further delays if
the signals need to be routed across the chip to their destination.
The sum of these delays is known as the
propagation delay
.
The mathematical relationship between the delays is
expressed by the following two equations which must be satisfied
for all paths within the chip:
propagation delay
e
setup time
clock period
þ
< ¼
propagation delay
hold time
> ¼
Where
is the mathematical less than or equal symbol, and
< ¼
is greater than or equal
There are more complex timing issues when signals cross from
one clock domain to another but these are usually handled by
specially designed library components.
A hardware design where these equations are satisfied for all
signals on the chip is said to
meet timing
. A design which does not
meet timing will usually fail in subtle and unexpected ways so
further debugging is not usually productive.
> ¼
21.1.1 Check that the Design Meets Timing
During synthesis the layout tool will place the logic within the
chip and then run a timing analysis to check that the design
meets the setup and hold requirements of the chip that will
implement it. If these requirements are not met, the tool will
