Biomedical Engineering Reference
In-Depth Information
present the state of the register on the screen as one line. Based on the emulator, the
debugger was created by Masao Kumagishi, a colleague at WACOM, and was used
to prepare the programs for the preliminary processing of images and to extract
features in the recognition programs for handwritten words and characters. We used
the emulator to analyze different structures of neural networks.
7.2.3 The Block Diagram of B-512
The block diagram is represented in Fig.
7.2
. CU is the control unit; SRAM
1
is the
random access memory for storing the neurocomputer's programs; SRAM
2
is
the random access memory for storing data; LMs are the logical modules; DRAM
is the dynamic memory whose size for each module is 256 K x 512 bits; and PC is
the personal computer, which enables interfacing with the neurocomputer.
The basic difference between the neurocomputer B-512 and the neurocomputer
NIC is that the quantity of operations needed for the simulation of specific neural
network functions is increased in B-512. The number of such operations includes
the hardware procedure for the calculation of a quantity of unit bits in the vector of
the activity of neurons.
The calculation of a quantity of 1s in the 512-bit vector is carried out with one
instruction whose duration is approximately 1
s, whereas with NIC, it is necessary
to carry out 512 sequential shifts of the vector for this purpose, demanding about
100
m
s. Another operation of this type is automatically searching for the numbers of
active neurons and writing these numbers into the memory SRAM
2
. These numbers
are used to select the lines from the matrix of synaptic weights. The selection of the
necessary line also is achieved with one instruction. B-512 uses a more developed
system for addressing dynamic memory, which makes it possible to form the index
registers that are necessary to organize the cycles.
One of the distinctive features of B-512 is the formation of virtual counters for
determining the input activity of neurons. NIC makes it possible to use counters
with depths not exceeding eight bits; the depth of the counters of B-512 is
m
SRAM
1
LM
1
LM
2
LM
8
CU
PC
DRAM
1
DRAM
2
DRAM
8
Fig. 7.2 The structure of the
neurocomputer B-512
SRAM
2
