Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 70

Significance-compression cache : Following in the footsteps of Yang et al. work, Kim et al.
[ 141 ] propose a scheme where lines are compressed using sign compression. Again, two com-
pressed lines can fit in the space of one, which means that the compression ratio must be at least
50%. For this to happen, all 32-bit words in a line must be sign-compressed to 16 bits. Although
this is possible, it is not very common. To increase the chances of fitting two lines into one,
extra space is provided in the data array for words that cannot be compressed by significance
compression. According to Kim et al [ 141 ], the inclusion of the extra space to accommodate
just one incompressible word per line makes a significant difference in the opportunities for
compression. Tolerating 25% incompressible data in cache lines yields energy savings on a par
with those in CC (about 23%) and for the same reasons.
4.4.4 Instruction Compression
Hines, Green, Tyson, and Whalley proposed the equivalent of the frequent value cache for
instructions [ 100 ]. They observe that, similarly to data, instructions too exhibit locality: a small
number of static instructions appear quite frequently in the dynamic stream. An impressive
80% of the dynamic stream in the MiBench suite can be easily captured with 64 different static
instructions. These can be stored in a dictionary—called Instruction Register File (IRF)—
similar to the frequent value dictionary. All instances of the frequent instructions in the code
can then be replaced by their index to the dictionary. This results in code compression, improved
fetch bandwidth, and energy savings. An innovation in their scheme is that the instructions in
the dictionary are parametrizable in their immediate field, so a few variations of the instruction
appearing in the static code can be covered by a single IRF entry. Hines et al. report that the
benefit in performance is not substantial, but the reduction in I-Fetch energy can reach 37%
for the MiBench [ 100 ] benchmark suite.
4.5 IDLE-CAPACITY SWITCHING ACTIVITY
Idle-capacity switching activity is essentially wasted activity related to out-of-order execution.
Similarly to the idle-width activity at the operation level, it appears because processor resources
(instruction queues, load/store queues, reservation stations, reorder buffers, caches, etc.) are
over provisioned to support a high-instruction throughput for target workloads.
Not every program, however, achieves the maximum instruction throughput and utilizes
these resources to full extent. This results in excessive power consumption for the achievable
performance. By re-balancing—most often resizing— processor resources to fit program needs,
power consumption can be trimmed to be commensurable to the attained performance. This is
the overarching goal of the techniques presented in this and the following three sections.