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TABLE 4.4: Estimated Energy Growth Parameters
(Adapted From [ 252 ])
γ =
.
Register Rename Logic
1
1
γ =
.
Instruction Issue Window
1
9
γ =
.
Memory Disambiguation Unit
1
5
Multiported Register File
γ =
1
.
8
Data Bypass Mechanisms
γ =
1
.
6
Functional Units a
1
a Power consumed by a functional unit is largely
independent of the issue width.
γ =
0
.
4.5.1 Power-inefficiency of Out-of-order Processors
What we call idle-capacity switching activity is intuitive to anyone who has studied the workings
of an out-of-order processor: large structures, often using content addressable memory, are
provided for peak performance, but typically underutilized. To further increase performance,
these structures must be enlarged, but the resulting increase in performance pales in comparison
to the increase in power and area. It was not until 2000, when Zyuban and Kogge put this
intuition into a formalism and showed that out-of-order processors are inherently power-
inefficient [ 252 ].
But what do we mean by “power-inefficient?” Zyuban and Kogge argue that a micro-
architecture is energy-efficient if its energy consumption increases commensurably with its IPC
(instructions per cycle) when the microarchitecture is scaled in its issue width.
To support this formally, Zyuban and Kogge set out and develop energy models for
the key structures (register rename table, bypass mechanism, instruction window, load/store
window, register file, and functional units) in an out-of-order processor. By analyzing energy
consumption as the issue width of the machine is increased, they derive an “energy growth”
factor for each structure. This factor shows how the energy-per-instruction grows as a function
of the issue width. Table 4.4 shows their estimates for the energy growth factor [ 252 ].
The energy-per-instruction growth for a particular structure can then be described as
(IW) γ ,
E i
where IW is the issue width and
γ
is the structure's energy growth factor. For instance, the
 
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