Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 60

FIGURE 4.7: The width of operands in SPECint95 for the 64-bit Alpha ISA From [ 37 ], Copyright
1999 IEEE.

2. By packing more than one narrow-width operation in the full width of the hardware.

Although this does not reduce power, it improves the performance and energy per
operation, resulting in better EDP.

Although these two techniques can share a common infrastructure in determining
narrow-width operands, each serves a different purpose—the first directly reduces power while
the second aims to increase performance. Both can co-exist in an implementation and either
one can be activated at any given time according to system-wide needs. There is also the
possibility of using both techniques concurrently, packing operations whenever possible but
disabling high-order bits of the ALU when there is only a single (narrow-width) operation
passing through.
Dynamically detecting narrow-width operands : Data in Figure 4.7 show that applications
have operands whose significant bits span the full range of bit widths. 3 So where is the line
drawn between narrow and wide? Initially, a fixed division at 16 bits was proposed: anything
16-bit wide or less is defined as narrow width and is treated as a 16-bit quantity; anything
greater than that is taken to be a full 64-bit operand [ 37 ]. As Figure 4.7 attests, this division
defines about one-half of the operands as narrow.
The detection of narrow-width operands is accomplished dynamically (although static
compiler analysis can also be a useful tool). Every value created in the ALU or loaded from the
cache is checked for its effective size. If 48 of its leading bits are all zeros or ones (for a two's
complement negative value), it can be represented and manipulated with just its lower 16 bits.
In this case, the value is tagged as narrow. A single bit “width” tag follows the value throughout
the machine.
Value gating: disabling the unused width : This technique directly reduces power by elimi-
nating useless switching. This is done by disabling switching in the unused parts of the ALU

3 Note that, for now, we assume that significant bits are strictly low-order bits. Subsequently, we relax this restriction.