Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 59

occurring operations. It is specific to operations, i.e., it appears when operations are performed—
whether ALU or memory operations (e.g., cache reads and writes). The main approach to
address this type of activity is to dynamically detect narrow-width operands and to either adapt
the width of the machine accordingly or, alternatively, pack multiple narrow-width operations
together. This goes for both the datapath, which we discuss here, and the caches discussed in
(Section 4.4).
The meaning of “narrow-width” has changed over time. Starting from a simple
definition—a value having only few significant bits in the low-order bit positions—the term
evolved to significance compression by relaxing some of the initial constraints; full-fledged frequent
value compression , that creates “narrow values” in caches, is a small step further.

4.3.1 Narrow-Width Operands
One of the most prominent characteristics of a processor is the data width for which it is
designed and built. While there are plenty of older-generation low-power, low-performance,
8-bit processors, most recent designs are either 32- or 64-bits wide. Quite often, however, this
width is not exercised in operations. For instance, most address offsets are small and can easily
fit in 16 or even 8 bits [ 96 ], so address arithmetic does not use all of the provisioned width of
the machine. The difference between the provisioned width and the width of commonly used
operands is increased with the move to 64-bit architectures where most of the width of the
datapath remains unused.
Multimedia applications also use many small operands. In fact, this has been the moti-
vation behind SIMD ISA extensions such as Intel's MMX and SSE/2/3, IBM's AltiVec, and
others [ 187 , 66 ]. These multimedia ISA extensions pack multiple sub-word operands in the
width of the machine and operate on all of them in parallel.
Brooks and Martonosi were among the first to propose techniques addressing Idle-
Width switching activity [ 37 ]. The motivation in their work is the abundance of narrow-width
operands in integer and multimedia applications. Figure 4.7 reproduces some of the relevant
statistics from their work for applications in the SPECint95 and the MediaBench benchmark
suites. The statistics show operand widths in the 64-bit Alpha ISA (with the DEC cc compiler
using aggressive optimizations). The left graphs show that a respectable portion (50%) of the
operations have both their operands “narrow” (16-bit wide or less). Furthermore, very few
operations have operands wider than 33 bits in a 64-bit machine (middle graph).
Exploiting narrow-width operands can be done in one of two ways:

1. By disabling the unused width of the hardware and eliminating switching in the

hardware slice that does not carry significant bits.