Using Voltage and Frequency Adjustments toManage Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 43

FIGURE 3.9: Pipeline recovery with global clock gating. A timing error in the EX stage results in the
MEM stage receiving the correct value too late. Global clock gating stops the whole pipeline so the
correct value can be restored in the Razor flip-flops. Operation then resumes one cycle later with the
correct values. Reproduced from [ 73 ]. Copyright 2003 IEEE.
with the correct values. This guarantees forward progress since a faulting instruction simply
continues execution in the next pipeline stage with the correct value. This technique is shown
in Figure 3.9.
If global clock-gating is not possible in an aggressively clocked design due to impact
on the cycle time, the second alternative technique: a counterflow pipelined approach—which
scales well with clock cycle—can be used (Figure 3.10). In this case, the faulting Razor flip-flop
distributes a bubble signal toward the end of the pipeline and a flush signal toward its front.
The bubble ensures that the faulting instruction will take an additional cycle to complete its
remaining stages, while the instructions following the faulting instruction are flushed.
Besides the timing errors that are detected by the Razor flip-flop, there is also a more
serious error that can happen—albeit with a very small probability. This is when the Razor
flip-flop detects that its error signal, after a timing error, is potentially in a meta-stable state.
In this case, the Razor flip-flop raises a panic signal (two cycles after the actual timing error)
to invoke higher-level control. Such an error is treated as a mis-speculation. A panic signal
from the faulting Razor flip-flop flushes the whole pipeline, including the faulting instruction,
restores the correct state, and replays the affected instructions.
FIGURE 3.10: Counterflow recovery of the pipeline after a timing fault. Flush and bubble signals are
distributed from the faulting Razor flip-flop toward the the front- and the back-end of the pipeline,
respectively. Reproduced from [ 73 ]. Copyright 2003 IEEE.