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power at that point. While the
V
dd
V
T
difference determines switching speed, maximum
gains in power consumption come from a combined adjustment of the two. Three independent
studies come to the same conclusion.
−
Duarte, Vijaykrishnan, Irwin, Kim, and McFarland study the impact of scaling on a
number of approaches for dynamic power reduction [
70
]. Among their experiments
they simultaneously scale the supply voltage (
V
dd
) and the body-to-source bias voltage
(
V
bs
), i.e., they simultaneously perform DVS and ABB. Their study is not constrained
in any variable, meaning that they examine a wide spectrum of possible values for the
two quantities. Their results show a clear advantage over DVS alone.
The work of Martin, Flautner, Mudge, and Blaauw combines DVS and Adaptive Body
Biasing to lower both dynamic and static power of a microprocessor during execution
[
163
]. They derive a closed-form formula for the total power consumption, expressing
it as a function of
V
dd
and
V
bs
(the body-to-source bias controlled by ABB). The
formula is the following:
C
eff
V
dd
V
dd
K
3
e
K
4
V
dd
e
K
5
V
bs
P
=
f
+
+|
V
bs
|·
I
j
,
where,
K
3
,
K
4
,and
K
5
are constants derived from simplifications made by expressing
V
T
as a function of
V
dd
and
V
bs
. The formula also includes a term for junction leakage
(
I
j
) which the authors consider important in this situation. In a similar manner, they
arrive at the following formula for the frequency,
f
:
(
L
d
K
6
)
−
1
V
th
1
)
a
f
=
((1
+
K
1
)
V
dd
+
K
2
V
bs
−
,
where
K
1
,
K
2
,
K
6
,and
V
th1
, are constants derived from approximations,
L
d
is the
depth of the logic path in relation to an inverter, and
a
is the exponent of the alpha-
power delay model of an inverter (here
a
1). As it is evident from the above formula,
f
—performance—is a linear function of
V
dd
and
V
bs
.
Martin et al. use the system-level technique of automatic performance setting
presented in Chapter 3 as a DVS-only technique (Section 3.2). In this technique,
deadlines are derived from monitoring system calls and interprocess communication.
The performance setting algorithm sets the processor frequency for the executing
workload so as to not disturb its real-time behavior.
Solving the system of the two equations above for a given performance setting,
Martin et al. are able to estimate the most profitable combination of
V
dd
and
V
bs
to
maximize power consumption savings. The approach can deliver savings
over
DVS
alone of 23% in a 180 nm process and 39% in a (predicted) 70 nm process [
163
].
=
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