Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 171

mode) since it expects that eventually instructions are going to be reused. While the other two
combinations of strategies and mechanisms are also possible (i.e., conservative with drowsy and
optimistic with gated- V dd ), they are not as effective.
Figure 5.17 shows the behavior of a combined hybrid strategy where the optimistic and
conservative strategies are used together. The hybrid strategy performs the best among all the
other complier strategies. It also outperforms both the (state-destroying) decay and the drowsy
techniques (with a fixed 4Kc decay interval) in terms of EDP in eight out of ten programs
[ 246 ].
5.4 ARCHITECTURAL TECHNIQUES BASED ON V T
The root of the exponential increase in subthreshold leakage can be traced to the lowering of
the threshold voltage, V T , as a result of technology scaling. Lowering the V T is a matter of
performance: device speed depends on the difference between the supply voltage, V dd ,andthe
threshold voltage V T (see Section 5.1.1). This leads to a classic trade-off between speed and
power that can be exploited to reduce the overall leakage consumption.
There are two broad approaches that exploit this trade-off, depending on whether V T
can be manipulated dynamically or is set at the design or manufacturing stage. In both cases, a
low V T yields increased speed at the expense of higher power consumption, whereas a high V T
reduces power consumption but also speed.
For the dynamic V T technologies the most interesting tradeoff happens in relation to
dynamic voltage scaling. Both V dd and V T scaling affect the device speed. V dd scaling reduces
dynamic power, whereas (upwards) V T scaling reduces leakage power. The question then
becomes, what to scale and how much for a given frequency of operation. This depends on the
relative strength of the dynamic versus leakage power. Multiple studies have shown that one
has to simultaneously scale both quantities to achieve the best possible results.
For the static, multiple- V T technologies, such as MTCMOS, two popular design
methodologies are generally followed.
The first relies on transistor stacking: a block of low- V T (high-leakage, high-speed)
transistors are stacked with a high- V T (low-leakage, low-speed) transistor. The high-
V T transistor is inserted between the high-speed logic block and one of the power rails
(commonly the ground rail). When it is turned off, it disconnects the logic block from
power, virtually eliminating leakage.
The second populates non-critical paths of a circuit with high- V T , low-leakage, tran-
sistors if there is enough slack to accommodate the increased latency [ 69 ]. Finally, in
memory designs, asymmetric cells using high- V T and low- V T devices can save leakage
depending on the stored bits [ 17 ].