Managing Static (Leakage) Power - Computer Architecture Techniques for Power-Efficiency - page 133

drowsy mode , manipulate voltage across transistor terminals (source and drain). This affects
the magnitude of leakage reduction, the latency in switching leakage modes, and the ability
to retain state in the low-leakage mode. The third class of low-level mechanisms manipulates
the transistor threshold voltage ( V T ) which can dramatically decrease leakage but at the cost of
reduced device speed.
It is important to note here that the techniques presented in this chapter address a specific
type of leakage, called subthreshold leakage . Another type of leakage, called gate oxide leakage ,is
not addressed architecturally but rather at the process level. To gain a better understanding of
the structure of this chapter as well as the difference in the two types of leakage, the following
section (Section 5.1) delves into the underlying mechanics of leakage.

5.1 A QUICK PRIMER ON LEAKAGE POWER
Static power is so called because it is consumed by every transistor even when no active switching
is taking place. In older technologies (e.g., NMOS, TTL, ECL, etc.) it is an inherent problem,
because a path from V dd to ground is open even when transistors are not switching. With the
advent of CMOS, static power became less of a concern because the Complementary gate design
prevents open paths from V dd to ground.
Unfortunately, static power resurfaced in CMOS in the form of leakage power. In the latest
process generations leakage power increases exponentially, principally because of reductions in
the threshold voltage. Leakage power increased to levels never seen before in CMOS—levels
comparable to the dynamic (switching) power consumption—when technology scaling entered
the deep-submicron territory in feature size ( < 180 nm). Currently, 20-40% of the total power

consumption is attributed to leakage power.
CMOS static power arises due to leakage currents . The total leakage current ( I leak )times
the supply voltage gives the static power consumption, P leak :

= × .

P leak V I leak

Leakage currents are a manifestation of the true analog nature of transistors, as opposed
to our idealized view of them as perfect digital switches. The state of a transistor (on or off)
is controlled by the voltage on its gate terminal. If this voltage is above the threshold voltage
( V T ) the channel beneath the gate conducts, allowing current in the on state ( I on ) to flow from
the source ( V dd ) to the drain (GND, ground). In the opposite case (gate voltage below V T ), we
like to think that the transistor is off (perfect insulator). But in reality transistors leak: leakage
currents flow even in their off state. This is evident in the I - V curve where current flows even
below the threshold voltage where the device is supposed to be “off.”
The current that flows from source to drain when the transistor is off is called sub-threshold
leakage. But that is not all. There are five more types of leakage: reverse-biased-junction