Information Technology Reference
In-Depth Information
TABLE 5.1: Structure of the Leakage Reduction Tehniques in this Chapter.
Low Level
High-Level
Section
Mechanism
Techniques
Characteristics
Stacking effect
and gated V dd :
sleep transistor
cuts off power
Dynamically resized cache
(DRI) [ 239 ], cache decay
[ 127 ], adaptive mode
control (AMC) [ 250 ],
functional unit decay [ 105 ]
Non-state-preserving
(state-destroying)
Significant leakage
reduction
Power-up latency: 10's
of cycles
Section 5.2
Drowsy effect:
scales supply
voltage to
reduce leakage
Drowsy caches [ 77 , 137 ],
drowsy instruction caches
[ 138 , 139 ], hybrid
approaches (decay
State-preserving
Medium leakage
reduction
Power-up latency:
Section 5.3
+
<
10
drowsy) [ 164 ],
temperature-adaptive
approaches [ 129 ],
compiler approaches &
hybrids [ 246 ]
cycles
Threshold voltage
( V T )
manipulation:
Dynamic
Combined V dd
(e.g., DVFS) and V T
(e.g., Adaptive Body
Biasing—ABB) scaling
[ 163 , 231 , 70 ]
Significant leakage
reduction
Section 5.4
Static
MTCMOS Functional
Units [ 69 ], Asymmetric
Memory Cells [ 17 , 18 ]
 
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