Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 96

Segmented into
4 segments

Global bit-line with
bypass switches

Activation of a single
segment Original Long bit-line

Bypass Switch

c
c

c
c

c
c

c
c

c
c

c
c

c
c

c
c

c
c

c
c

c
c

c
c

Selected by
predecoding

c
c

c
c

c
c

c
c

Long bit-line

Bypass Switch

FIGURE 4.22: Bit-line segmentation. Only one bit-line per cell (c) and the corresponding pass transistor
are shown. The original bit-line carrying 8 cells is partitioned in 4 segments each carrying 2 cells. The
4 segments attach to a new global bit-line via bypass switches. The bypass switches control dynamically
which segment drives the global bit-line. Adapted from [ 83 ].

and can be easily made power-efficient. This leaves the area overhead as the main cost for the
Miss Tags which Zhang and Asanovic estimate to be about 10% for a 32KB cache [ 243 ].
The performance difference from resizing the cache is estimated as the difference of the
misses of the resized cache and the full cache. The policy is to downsize the cache as much as
possible without letting this difference exceed an empirically derived limit. Zhang and Asanovic
report that MTR yields a significant reduction in the dynamic energy of the order of 28% for
the data cache (34% for the instruction cache) compared to a full-size CAM-tag cache.

☞ bit-line segmentation : Bit-line segmentation applies to long bit-lines in SRAM arrays

[ 125 , 83 ]. Such bit-lines are connected via pass transistors to a large number of memory
cells. The capacitive load due to the diffusion capacitance of the pass transistors in addition
to the capacitance of the wire itself, significantly adds to the power (e.g., precharge power
and sense power) needed to drive such bit-lines. The solution is to break the bit-line in k
segments, each carrying a fraction of the cells of the original bit-line (see Figure 4.22). In
contrast to wire segmentation, bit-line segments are not stringed together with repeaters.
Instead, a new global bit-line is introduced to carry the result from each of the bit-line
segments.
Each segment of the original bit-line attaches to the global bit-line via a bypass switch
(Figure 4.22). These switches dynamically control which bit-line segment drives the global
bit-line. Part of the address is predecoded to allow only the relevant bit-line segment on the
global bit-line. The power benefit in this case comes from activating only a small segment