Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 95

RAM-tag Cache CAM-tag Cache

(4) sets

(4) associative ways CAM-tags

RAM-tags

bit-lines

bit-lines

sense amps

sense amps

FIGURE 4.21: Bit-line organization in RAM-tag and CAM-tag caches. Bit-lines in RAM-tag caches
run across sets. Bit-lines in CAM-tag caches run across ways (not sets).

(in the number of its ways) independently of any other set. This holds regardless on whether a
set corresponds to a single bank (as depicted in Figure 4.21) or shares a bank with other sets.
Using bit-line segmentation, a set can be partitioned into a small number of partitions,
each encompassing a number of ways. For example, partitioning a 32-way set into 8 partitions,
results in 4 ways (cache lines) per partition. In the Zhang and Asanovic work [ 243 ], resizing
is performed in steps of a single way (a single cache line) at a time. Gated- V dd —a technique
to reduce leakage—deactivates individual cache lines. However, only when all the cache lines
(ways) in a partition are deactivated can the bit-line segment of that partition be taken off the
global bit-line and all switching activity in the partition cease. In the example of the 32-way,
8-partition cache, only when all four cache lines of a partition are deactivated is the partition
itself deactivated.
The control policy for resizing is a classic performance-based feedback loop. What is
measured is whether resizing (upsizing or downsizing) leads to worse, better, or the same
performance. Depending on the measurement, resizing (up or down) is continued, reversed,
or postponed. The metric for performance is the number of misses in a time window of 128K
references [ 243 ]. One way to use this number would be to compare it to the number of
misses measured in the previous time window. But this would entail considerable uncertainty
in gauging the effect of a resizing decision on performance. This is because miss rate can vary,
not solely as a function of cache size, but as a result of program behavior as well.
Zhang and Asanovic propose something more reliable—albeit, at an additional cost. They
compare the number of misses of the resized cache to the number of misses that would arise in
the full-size cache. They do this by keeping a second (full) set of tags, called the Miss Tags , whose
sole purpose is to count the number of misses in the full-size cache. Miss Tags are only accessed
during misses. Since they serve only an accounting role they are not performance-critical