Civil Engineering Reference
In-Depth Information
Y. Saad and M. H. Schultz. GMRES: A generalized minimal resid-
ual algorithm for solving nonsymmetric linear systems.
SIAM
Journal on Scientific and Statistical Computing,
7(3):856-869,
July 1986.
[SS86]
[SS92]
T. G. Szymanski and N. Shenoy. Verifying clock schedules.
In
Proceedings of the IEEE/ACM International Conference on
Computer-Aided Design,
pages 124-131, 1992.
[SS01]
H. Su and S. S. Sapatnekar. Hybrid structured clock network con-
struction. In
Proceedings of the IEEE/ACM International Con-
ference on Computer-Aided Design,
pages 333-336, 2001.
[SS02]
S. S. Sapatnekar and H. Su. Analysis and optimization of power
grids.
IEEE Design and Test,
20(3):7-15, May-June 2002.
[SSBS92]
N. Shenoy, K. J. Singh, R. K. Brayton, and A. Sangiovanni-
Vincentelli. On the temporal equivalence of sequential circuits.
In
Proceedings of the ACM/IEEE Design Automation Conference,
pages 405-409, 1992.
[SSE95]
I. Y. Spillinger, L. Stok, and G. Even. Improving initialization
through reversed retiming. In
Proceedings of the European Design
and Test Conference,
pages 150-154, 1995.
[SSF95]
H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn. Speed-
ing up pipelined circuits through a combination of gate sizing and
clock skew optimization. In
Proceedings of the IEEE/ACM Inter-
national Conference on Computer-Aided Design,
pages 467-470,
1995.
[SSP99]
V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi. MARSH:
Min-area retiming with setup and hold constraints. In
Proceedings
of the IEEE/ACM International Conference on Computer-Aided
Design,
pages 2-6, 1999.
[SSP02]
V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi. Fast and
exact transistor sizing based on iterative relaxation.
IEEE Trans-
actions on Computer-Aided Design of Integrated Circuits and Sys-
tems,
21(5):568-581, May 2002.
[SSWN97]
S. Simon, C. V. Schimpfle, M. Wroblewski, and J. A. Nossek.
Retiming of latches for power reduction of DSP design. In
Pro-
ceedings of the IEEE International Symposium on Circuits and
Systems,
pages 2168-2171, 1997.
[ST83]
T. Sakurai and K. Tamaru. Simple formulas for two- and three-
dimensional capacitance.
IEEE Transactions on Electron Devices,
ED-30(2):183-185, February 1983.
