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clock skew. IEEE Transactions on VLSI Systems‚ 4(2):286-291‚
June 1996.
J. L. Neves and E. G. Friedman. Buffered clock tree synthesis
with non-zero clock skew scheduling for increased tolerance to
process parameter variation. Journal of VLSI Signal Processing
Systems for Signal, Image and Video Technology, 16(2/3): 149-
162, June/July 1997.
[NF97]
I. Neumann and W. Kunz. Placement driven retiming with a
coupled edge timing model. In Proceedings of the IEEE/ACM
International Conference on Computer-Aided Design, pages 95-
102, 2001.
[NK01]
J. W. Nilsson and S. A. Riedel. Electric Circuits. Prentice-Hall,
Upper Saddle River, NJ, 6th edition, 2000.
[NR00]
[NS04]
V. Nookala and S. S. Sapatnekar. A method for correcting the
functionality of a wire-pipelined circuit. In Proceedings of the
ACM/IEEE Design Automation Conference, 2004.
A. Odabasioglu, M. Celik, and L. T. Pileggi. PRIMA: Pas-
sive reduced-order interconnect macromodeling algorithm. IEEE
Transactions on Computer-Aided Design of Integrated Circuits
and Systems, 17(8):645-654, August 1998.
[OCP98]
A. Odabasioglu, M. Celik, and L. T. Pileggi. Practical consid-
erations for passive reduction of RLC circuits. In Proceedings
of the IEEE/ACM International Conference on Computer-Aided
Design, pages 214-219, 1999.
[OCP99]
M. Orshansky and K. Keutzer. A general probabilistic framework
for worst case timing analysis. In Proceedings of the ACM/IEEE
Design Automation Conference, pages 556-561, June 2002.
[OK02]
M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu. Im-
pact of spatial intrachip gate length variability on the performance
of high-speed digital circuits. IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, 21(5):544-553,
May 2002.
P. R. O'Brien and D. T. Savarino. Modeling the driving-point
characteristic of resistive interconnect for accurate delay estima-
tion. In Proceedings of the IEEE/ACM International Conference
on Computer-Aided Design, pages 512-515, 1989.
[OS89]
K. Okada, K. Yamaoka, and H. Onodera. A statistical gate-
delay model considering intra-gate variability. In Proceedings of
[OYO03]
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