Civil Engineering Reference
In-Depth Information
International Conference on Computer-Aided Design‚
pages 216-
219‚ 1997.
[MS98a]
N. Maheshwari and S. S. Sapatnekar. Efficient minarea retiming
for large level-clocked circuits. In
Proceedings of the Conference
on Design Automation and Test in Europe,
pages 840-845, 1998.
[MS98b]
N. Maheshwari and S. S. Sapatnekar. Efficient retiming of large
circuits.
IEEE Transactions on VLSI Systems,
6(1):74-83, March
1998.
N. Maheshwari and S. S. Sapatnekar. Optimizing large multi-
phase level-clocked circuits.
IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems,
18(9):1249-1264,
September 1999.
[MS99]
S. Malik, E. M. Sentovich, R. K. Brayton, and A. Sangiovanni-
Vincentelli. Retiming and resynthesis: Optimizing sequential net-
works with combinational techniques. In
Proceedings of the 23rd
Anual Hawaii International Conference on System Sciences,
pages
397-406, 1990.
[MSBS90]
S. Malik, E. M. Sentovich, R. K. Brayton, and A. Sangiovanni-
Vincentelli. Retiming and resynthesis: Optimizing sequential
networks with combinational techniques.
IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems,
10(1):74-84, January 1991.
[MSBS91]
[MSM04]
M. Mneimneh, K. A. Sakallah, and J. Moondanos. Preserving
synchronizing sequences of sequential circuits after retiming. In
Proceedings of the Asia/South Pacific Design Automation Con-
ference,
2004.
[Nag75]
L. W. Nagel. Spicc2: A computer program to simulate semicon-
ductor circuits. Technical Report ERL M520, Electronics Research
Laboratory, University of California, Berkeley, Berkeley, CA, May
1975.
[Nai02]
S. Naidu. Timing yield calculation using an impulse-train ap-
proach. In
Proceedings of 15th International Conference on VLSI
Design,
pages 219-224, January 2002.
R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa. Genera-
tion of performance constraints for layout.
IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems,
8(8):860-874, August 1989.
[NBHY89]
[NF96]
J. L. Neves and E. G. Friedman. Design methodology for syn-
thesizing clock distribution networks exploiting nonzero localized
