References - Timing - page 270

[JC93] D. Joy and M. Ciesielski. Clock period minimization with wave

pipelining. IEEE Transactions on Computer-Aided Design of In-
tegrated Circuits and Systems‚ 12(4):461-472‚ April 1993.

[JH01] X. Jiang and S. Horiguchi. Statistical skew modeling for general

clock distribution networks in presence of process variations. IEEE
Transactions on VLSI Systems‚ 9(5):704-717‚ October 2001.

J. A. G. Jess‚ K. Kalafala‚ S. R. Naiddu‚ R. H. J. M. Otten‚ and
C. Visweswariah. Statistical timing for parametric yield prediction
of digital integrated circuits. In Proceedings of the ACM/IEEE
Design Automation Conference‚ pages 932-937‚ June 2003.

[JMDK93] H.F. Jyu‚ S. Malik‚ S. Devadas‚ and K.W. Keutzer. Statistical

timing analysis of combinational logic circuits. IEEE Transactions
on VLSI Systems‚ 1(2):126-137‚ June 1993.

N. Jouppi. Derivation of signal flow direction in MOS VLSI.
IEEE Transactions on Computer-Aided Design of Integrated Cir-
cuits and Systems‚ CAD-6(5):480-490‚ May 1987.

[Jou87a]

[Jou87b] N. P. Jouppi. Timing analysis and performance improvement of

MOS VLSI design. IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems‚ CAD-4(4):650-665‚ July 1987.

[JS91] Yun-Cheng Ju and Resve A. Saleh. Incremental techniques for

the identification of statically sensitizable critical paths. In Pro-
ceedings of the ACM/IEEE Design Automation Conference‚ pages
541-546‚ 1991.

[JSK90] M. A. B. Jackson‚ A. Srinivasan‚ and E. S. Kuh. Clock routing for

high-performance IC's. In Proceedings of the ACM/IEEE Design
Automation Conference‚ pages 573-579‚ 1990.

N. A. Kurd‚ J. S. Barkatullah‚ R. O. Dizon‚ T. D. Fletcher‚
and P. D. Madland. A multigigahertz clocking scheme for the
Pentium ® 4 microprocessor. IEEE Journal of Solid-State Cir-
cuits‚ 36(11):1647-1653‚ November 2001.

[KC66] T. I. Kirkpatrick and N. R. Clark. PERT as an aid to logic design.

IBM Journal of Research and Development‚ 10(2): 135-141‚ March
1966.

[KCR91] A. Kahng‚ J. Cong‚ and G. Robins. High-performance clock rout-

ing based on recursive geometric matching. In Proceedings of the
ACM/IEEE Design Automation Conference‚ pages 322-327‚1991.

K. Keutzer. DAGON: Technology binding and local optimiza-
tion by DAG matching. In Proceedings of the ACM/IEEE Design
Automation Conference‚ pages 341-347‚ 1987.

[Keu87]