RETIMING - Timing - page 207

illustrated in Figure 10.2. The circuit in Figure 10.2(a) requires two registers,
while that in Figure 10.2(b) requires only one register.
Therefore, one could apply retiming with the object of minimizing the num-
ber of registers in the circuit, while leaving the input-output latency un-
changed. This may be done without any constraint on the clock period
of the resulting circuit, or subject to a target clock period. The former is
called unconstrained minimum area retiming while the latter is referred to
as constrained minimum area retiming or simply minimum area retiming.
In practice, minimum area retiming is a more useful form of the retiming
transformation than minimum period retiming.
Power The power dissipated in a circuit depends on the product of the switch-
ing activity and the load capacitance at the output of a gate, summed over
all gates. Since registers can filter out glitches, altering their locations can
affect the switching activity at gate outputs; moreover, it can also alter the
load capacitance seen by the gates. Thus, retiming can change the power
dissipation of a circuit, and an appropriately chosen retiming may be used to
optimize the power by placing registers at nodes with high switching activity
values and high capacitive loads.
Testability The relocation of registers can change the state encoding in se-
quential circuits, thus affecting the test generation time and the number of
redundant faults. The repositioning of registers also affects the length of the
scan chains required for partial or full scan designs. Retiming can, therefore,
be used to improve the testability of sequential circuits.
Quality of logic optimization Most logic optimization techniques operate
on combinational logic blocks separated by register boundaries. Hence,
changing these register boundaries by retiming the registers affects the qual-
ity of results obtained by logic optimization.