RETIMING - Timing - page 206

edge-triggered circuits is presented. Finally, we discuss fast and efficient meth-
ods for retiming large edge-triggered and level-clocked circuits to minimize their
clock period.
10.1.1 Types of retiming
Retiming may be performed to improve the circuit behavior with respect to
several possible objective functions, some of which are outlined below.
Clock period Algorithmically, the simplest objective function used in retim-
ing is the minimization of the clock period. Since the clock period in a circuit
with edge-triggered FF's is given by the maximum combinational delay, the
FF's may be relocated to reduce the clock period. For the circuit shown
in Figure 10.1(a), with unit delay gates and edge-triggered FF's, the clock
period is 3 time units. If we relocate register F1 from the output of gate G3
to its input, we obtain the circuit in Figure 10.1(b), with a clock period of 2
units. Notice that the input-output behavior is left unchanged by retiming
since the output is produced after two clock cycles in both the original and
the retimed circuit. Thus, relocating registers can reduce the clock period of
a circuit, and retiming can be used to relocate registers with the objective of
minimizing the clock period. A retiming that minimizes the clock period of
a circuit is termed a minimum period retiming. Retiming a circuit to achieve
a specified target clock period is a special case of minimum period retiming,
and is often called specified-period retiming.
Area Since retiming does not affect the combinational part of the circuit, the
area overhead of the combinational logic remains constant under retiming.
The method may, however, affect the overall area of the circuit since it may
alter the number of registers in the circuit.
Two retimed versions of the same circuit could have the same input-output
behavior and clock period, but could use a different number of registers, as