Civil Engineering Reference
In-Depth Information
The remainder of this section presents three techniques for simultaneous
optimization of skews and transistor sizes.
9.4.1 A linear programming formulation
The set of long path constraints in the presence of clock skews can be seen
from Inequation (9.4) to be linear in the skew variables and the gate delays.
If the gate delays could also be represented in terms of linear functions of
the transistor sizes‚ then the set of timing constraints on a circuit would be
linear. This idea forms the basis of the linear programming formulation [CSH93‚
CSH95] discussed in this section.
The delay of a gate is represented as a convex piecewise linear function of
its own size and that of its fanout gates. The delay
of a gate with size
and with fanout gates of sizes
can be
represented using a convex piecewise linear function with
regions as:
