CLOCKING AND CLOCK SKEW OPTIMIZATION - Timing - page 194

paragraph‚ this sum is a linear function of P of the form the lower
bound on the clock period is updated to to ensure that this cycle will
not have a positive weight. This procedure can be repeated on every cycle in
the graph of predecessor edges; note that the number of edges in such a graph
is O (| V |)‚ where | V | is the number of vertices‚ which means that this can be
performed inexpensively. Similarly‚ if the clock period is feasible‚ the graph of
predecessor edges may be used to update the upper bound on the clock period
by exploring the amount by which the clock period could be lowered before the
predecessor graph would be altered.
Note that the solution to the problem of clock period minimization corre-
sponds to the maximum P over all positive cycles; it is‚ in general‚ not possible
to find this maximum in polynomial time since the number of cycles could be
exponential in the number of vertices. However‚ it has been seen that from
a practical standpoint‚ the back-pointer procedure works well in reducing the
amount of computation.

9.4 CLOCK SKEW OPTIMIZATION WITH TRANSISTOR SIZING

In the discussion so far‚ it has been assumed that the delay of each combi-
national path is fixed. However‚ the drive strength of gates can be altered
by transistor sizing [SK93]‚ thereby changing the combinational path delays.
Treating clock skew optimization and transistor sizing as separate optimizations
is liable to lead to a suboptimal solution‚ and a synergistic blend of the two
procedures can greatly improve the cost-performance tradeoff for the circuit.
To illustrate this‚ consider a pair of combinational stages separated by
latches‚ as shown in Figure 9.12(a). We will consider area as the cost func-
tion here‚ but the same idea is valid for other correlated cost functions such as
power. If only the sizing transformation were to be applied‚ the nature of the
cost-delay tradeoff curve for each stage would be as shown in Figure 9.12(b). If
the timing specification on were stringent‚ then the optimal sizing solution
would lie beyond the knee of the curve‚ at a point such as point A. Similarly‚
if the specifications on were loose‚ then the optimal solution might lie at
a point such as C. The cost of the sizing solution would then be [Area(A) +
Area(C)].
Now consider a situation where a small skew‚ S‚ is applied to the registers
between the two stages‚ allowing to borrow time from This would
lead to a looser specification on bringing the solution point from A to
B‚ and a tighter specification for Stg 2 ‚ moving its solution from C to D. The
cost of the overall sizing solution‚ [Area(B) + Area(D)]‚ can be seen to be
much smaller than the cost with zero skew‚ even for a small amount of cycle
borrowing‚ since the cost at the solution point A was well above the knee of
the curve 2 . Therefore‚ the judicious use of sizing in conjunction with deliberate
skew can deliver solutions of significantly better quality than sizing alone. It is
important to perform the two optimizations concurrently‚ rather than one after
another‚ to fully incorporate the mutual interactions between skew and sizing.