Civil Engineering Reference
In-Depth Information
Denoted the delay of the combinational block between them as
with
being the minimum delay and being the maximum delay. If
is the flip-flop hold time‚ the flip-flop setup time‚ and
P
the clock period‚
then in the presence of skews‚ the timing constraints take the following form
Long path constraints
To avoid “zero-clocking‚” the data from the current
clock cycle should arrive at
no later than a time
before the next
clock. Since the data leaves
at time
the latest time by which it will
reach
is
The long path constraint‚ shown in Figure 9.10‚
may be expressed as
Short path constraints
To avoid “double-clocking‚” the data from the next
clock cycle should arrive at
no earlier than a time
after the current
clock. The data leaves
at time
and‚ therefore‚ the earliest time it
can reach is
Thus‚ the short path constraint illustrated in
Figure 9.11 is
9.3.2 Clock period minimization
The problem of minimizing the clock period
P
by controlling the clock skew at
each flip-flop‚ subject to correct timing‚ can now be formulated as the following
