Civil Engineering Reference
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particularly interesting: a separate reference clock is distributed along with the
core clock distribution‚ and feedback clocks are provided from the end points of
the core clock distribution back to the DSK‚ as shown in Figure 9.8(b). A phase
detector in the DSK then samples the phase difference between the reference
clock and the local feedback clock‚ and a tunable delay circuit is used to adjust
the skew until it is removed. Early generations of the processor selected one
of several discrete delays by picking the appropriate tap from a delay line‚ but
more recently‚ fuse-based deskew has been employed.
9.3 CLOCK SKEW OPTIMIZATION
It has been demonstrated at the beginning of this chapter that the use of in-
tentional nonzero clock skews can speed up the clock period for a sequential
circuit since it facilitates cycle-borrowing. The work of Fishburn [Fis90] for-
malized an approach to find the optimal skews at each memory element in an
edge-triggered circuit‚ where the optimality was defined in terms of minimiz-
ing the clock period. The problem was posed as a linear program‚ and this
formulation is described in this section.
9.3.1 Timing constraint
s
Consider a combinational block in a sequential circuit‚ as shown in Figure 9.9.
Let and be a pair of flip-flops at the input and output‚ respectively‚
of the combinational block‚ with skews of
and
respectively.
