Civil Engineering Reference
In-Depth Information
and
E
is the set of edges (corresponding to connections among gates). If
represents the worst-case arrival time of a signal at the output of gate
then
for each gate, the delay constraint is expressed as
where gate
fanout
and
is the delay of gate
Therefore‚ the
transistor sizing problem can be framed as [CCW99]
Here, for primary output is the arrival time specification at the output,
and at primary input is the specified arrival time at the input (in the
most common case where a combinational block between flip-flops is being
considered, for all primary inputs For all other gates is the
arrival time at the output and is the delay of the gate. The rising and falling
arrival times may be considered separately within this framework. As before,
is a weight associated with the size of the transistor.
Thus, the number of delay constraints is reduced from a number that could,
in the worst case, be exponential in |
V
|, to one that is linear in |
E
|, by the
addition of
O
(|
V
|) intermediate variables.
Practically, the number of constraints can be substantially reduced even
over this, using a technique proposed in [VC99]. The essential idea of this
approach is based on the observation that the introduction of the intermediate
variables above does not
always
win over path enumeration. In cases where
subpath enumeration reduces the number of constraints, some constraints could
be combined, and the intermediate arrival time variables eliminated. As an
example, consider a case of a chain of three inverters, as shown in Figure 8.1,
and let us assume that the rise and fall delays are processed separately. The
circuit has two paths, and if the required delay at the output is then
assuming that the inputs are available at time 0, the constraints can be written
as
where and are‚ respectively‚ the rise and fall delays of gate On
the other hand‚ if intermediate arrival time variables are used‚ the number of
